从0到1：无线超声评估套件硬件架构解析

本文是《从0到1打造一款无线超声评估套件踩过的坑和总结的路》的续篇聚焦于评估套件的硬件构成与设计细节。一、硬件架构概述当前主流超声系统的硬件架构普遍采用以下框架AFE HV Pulser HV Switch FPGA USB/WIFI/PCIe各功能模块的典型选型如下模块代表器件供应商AFE模拟前端AD927x 系列ADIAFE模拟前端AFE58 系列TIPulser发射脉冲发生器HDL6M05584日立/ABLICPulser高集成度TX7332TIHV Switch高压开关ECN3297 系列日立/MicrochipFPGAZynq 7000 系列AMD原Xilinx数据传输USB 2.0/3.0 / WiFi / PCIe—二、核心BOM清单无线超声评估套件的核心物料清单如下组件型号功能说明FPGA SoCZYNQ7020 / ZYNQ7010ARM FPGA异构计算平台负责AFE控制、波束合成、信号处理与数据传输AFE器件AD92788通道完整信号链芯片集成LNAVGAAAF12位ADCI/Q解调器Pulser器件HDL6M055848通道3电平高压高速超声脉冲发生器Switch器件ECN329716通道高压模拟开关芯片无线模组高通5G AC WiFi模组802.11ac标准5GHz频段理论速率867Mbps~1.3Gbps系统工作流程系统启动后Linux系统运行于PS侧Processing System对PL侧Programmable Logic进行初始化配置超声数据通过DMA方式从PL传输至PS的DDR内存最终通过WiFi模组上传至PC实现实时成像。三、AFE选型详解AD9278AD9278是整套系统的核心芯片其选型理由如下高度集成单芯片集成8通道完整信号链——LNA低噪声前置放大器、VGA可变增益放大器、AAF抗混叠滤波器、12位ADC以及I/Q解调器低功耗TGC时间增益补偿模式下每通道功耗仅88mW40MSPSCW多普勒模式下低至32mW/通道小尺寸专为低成本、低功耗、便携式超声应用设计8通道架构配合标准线阵/凸阵探头覆盖绝大多数科研验证场景四、无线通信方案选择WiFi 5G AC802.11ac而非2.4GHz频段核心考量如下干扰少5GHz频段在医疗场景下干扰更少延迟低满足医疗成像对实时性的严苛要求高带宽理论速率867Mbps~1.3Gbps带宽优化策略原始RF数据量达Gbps级别直接实时上传存在瓶颈。当前采用两种解决方案在FPGA内完成波束合成后再传输图像数据数据量降至Mbps级别在FPGA内部缓存RF信号后集中上传适用于AFE前端评估场景五、硬件系统与交互设计系统由单板 电池 探头三部分组成。面板指示灯说明红灯电源指示灯黄灯工作状态指示灯中间按钮开关机控制无线连接长按开机按钮约3秒启动系统WiFi热点SSID为VisSonixAP-080默认密码12345678。上位机软件VisSonixAP双击APP.exe启动支持以下参数调节深度调节成像深度频率调节发射频率焦点调节发射聚焦位置六、FPGA约束与接口定义为便于后续扩展和测试硬件结构采用新的软排线连接方案。FPGA管脚约束set_property IOSTANDARD LVDS_25 [get_ports fpga_clk_*] set_property PACKAGE_PIN H16 [get_ports fpga_clk_p] set_property PACKAGE_PIN H17 [get_ports fpga_clk_n] set_property IOSTANDARD LVCMOS33 [get_ports ps_rxd] set_property IOSTANDARD LVCMOS33 [get_ports ps_txd] set_property PACKAGE_PIN P18 [get_ports ps_txd] set_property PACKAGE_PIN P15 [get_ports ps_rxd] set_property IOSTANDARD LVCMOS25 [get_ports sys_led] set_property PACKAGE_PIN J15 [get_ports sys_led] set_property IOSTANDARD LVDS_25 [get_ports {adc_din_p[*]}] set_property IOSTANDARD LVDS_25 [get_ports {adc_din_n[*]}] set_property IOSTANDARD LVDS_25 [get_ports adc_dclk_p] set_property IOSTANDARD LVDS_25 [get_ports adc_dclk_n] set_property IOSTANDARD LVDS_25 [get_ports adc_fclk_p] set_property IOSTANDARD LVDS_25 [get_ports adc_fclk_n] set_property PACKAGE_PIN L17 [get_ports adc_dclk_n] set_property PACKAGE_PIN L16 [get_ports adc_dclk_p] set_property PACKAGE_PIN K17 [get_ports adc_fclk_n] set_property PACKAGE_PIN K18 [get_ports adc_fclk_p] set_property PACKAGE_PIN C20 [get_ports {adc_din_p[7]}] set_property PACKAGE_PIN B20 [get_ports {adc_din_n[7]}] set_property PACKAGE_PIN B19 [get_ports {adc_din_p[6]}] set_property PACKAGE_PIN A20 [get_ports {adc_din_n[6]}] set_property PACKAGE_PIN E17 [get_ports {adc_din_p[5]}] set_property PACKAGE_PIN D18 [get_ports {adc_din_n[5]}] set_property PACKAGE_PIN D19 [get_ports {adc_din_p[4]}] set_property PACKAGE_PIN D20 [get_ports {adc_din_n[4]}] set_property PACKAGE_PIN E18 [get_ports {adc_din_p[2]}] set_property PACKAGE_PIN E19 [get_ports {adc_din_n[2]}] set_property PACKAGE_PIN F16 [get_ports {adc_din_p[3]}] set_property PACKAGE_PIN F17 [get_ports {adc_din_n[3]}] set_property PACKAGE_PIN M19 [get_ports {adc_din_p[0]}] set_property PACKAGE_PIN M20 [get_ports {adc_din_n[0]}] set_property PACKAGE_PIN M17 [get_ports {adc_din_p[1]}] set_property PACKAGE_PIN M18 [get_ports {adc_din_n[1]}] set_property PACKAGE_PIN L19 [get_ports adc_sclk] set_property PACKAGE_PIN L20 [get_ports adc_sdio] set_property PACKAGE_PIN K19 [get_ports adc_csb] set_property PACKAGE_PIN J19 [get_ports adc_stby] set_property PACKAGE_PIN F19 [get_ports adc_pdwn] set_property IOSTANDARD LVCMOS25 [get_ports adc_csb] set_property IOSTANDARD LVCMOS25 [get_ports adc_pdwn] set_property IOSTANDARD LVCMOS25 [get_ports adc_sclk] set_property IOSTANDARD LVCMOS25 [get_ports adc_sdio] set_property IOSTANDARD LVCMOS25 [get_ports adc_stby] set_property IOSTANDARD LVCMOS33 [get_ports hdl5584_tcen] set_property IOSTANDARD LVCMOS33 [get_ports {hdl5584_pulse[*]}] set_property PACKAGE_PIN T16 [get_ports {hdl5584_pulse[1]}] set_property PACKAGE_PIN R19 [get_ports {hdl5584_pulse[0]}] set_property PACKAGE_PIN W13 [get_ports {hdl5584_pulse[3]}] set_property PACKAGE_PIN Y16 [get_ports {hdl5584_pulse[2]}] set_property PACKAGE_PIN T14 [get_ports {hdl5584_pulse[5]}] set_property PACKAGE_PIN W14 [get_ports {hdl5584_pulse[4]}] set_property PACKAGE_PIN V12 [get_ports {hdl5584_pulse[7]}] set_property PACKAGE_PIN Y14 [get_ports {hdl5584_pulse[6]}] set_property PACKAGE_PIN T12 [get_ports {hdl5584_pulse[9]}] set_property PACKAGE_PIN U12 [get_ports {hdl5584_pulse[8]}] set_property PACKAGE_PIN R14 [get_ports {hdl5584_pulse[11]}] set_property PACKAGE_PIN T11 [get_ports {hdl5584_pulse[10]}] set_property PACKAGE_PIN T10 [get_ports {hdl5584_pulse[13]}] set_property PACKAGE_PIN P14 [get_ports {hdl5584_pulse[12]}] set_property PACKAGE_PIN T15 [get_ports {hdl5584_pulse[15]}] set_property PACKAGE_PIN Y17 [get_ports {hdl5584_pulse[14]}] set_property PACKAGE_PIN U17 [get_ports hdl5584_tcen] set_property IOSTANDARD LVCMOS33 [get_ports {hvmux_data[*]}] set_property IOSTANDARD LVCMOS33 [get_ports hvmux_le] set_property IOSTANDARD LVCMOS33 [get_ports hvmux_sclk] set_property IOSTANDARD LVCMOS33 [get_ports hvmux_clr] set_property PACKAGE_PIN U15 [get_ports hvmux_le] set_property PACKAGE_PIN U14 [get_ports hvmux_sclk] set_property PACKAGE_PIN U18 [get_ports hvmux_clr] set_property PACKAGE_PIN U19 [get_ports {hvmux_data[0]}] set_property PACKAGE_PIN N18 [get_ports {hvmux_data[1]}] set_property PACKAGE_PIN P19 [get_ports {hvmux_data[2]}] set_property PACKAGE_PIN N20 [get_ports {hvmux_data[3]}] set_property PACKAGE_PIN P20 [get_ports {hvmux_data[4]}]开源地址https://github.com/VisSonixAP/Ultrasound-AFE-Dev-Kit---------------------------------------------原创文章 版权©2026 VisSonixAP-欢迎转载 注明出处-有任何问题,欢迎致电-邮 箱:VisSonixAP163.com-公众号:VisSonixAP--------------------------------------------